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2.3 x 3.6 x 0.5 inches
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200 mA at 5V DC power
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High-Speed Delta-Sigma ADC (ADS1610)
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User Programmable Sample Rate, up to 10M SPS
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On-Chip Digital Filter Simplifes Anti-Alias
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User confgurable FIFO data size, up to 4MB.
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Stackable multi units sharing Sync, and Trigger.
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On-board oscillator or external host clock.
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Driven be 16-bit TERN controllers
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Support ADC read, ADC-FIFO, FIFO-read modes
The GR16 can be installed on any TERN Engine controller, including the
A-Engine86-P shown here.
ADC Sampling
Three operation modes are available: ADC-read, ADC-FIFO, and FIFO-read.
In ADC-read mode, an application running on the host can read the 16-bit ADC data at any time. Sampling rate would be limited to CPU and application processing speed.
In ADC-FIFO mode, the board can sample at far faster speeds (up to 10M samples per second). This data is recorded into the on-board FIFO SRAM. The ADC-FIFO operation is done entirely in hardware, without using any host CPU time.
Finally, the system can be set to FIFO-read mode. The host CPU can then read as much FIFO data as desired via I/O or DMA access.
The ADC sampling clock can be driven by on-board clock oscillator, or an external clock. With a 60MHz on-board oscillator, the sample rate is 10MHz maximum. User can control the sampling rate by using variable external clock, or selecting different dividers using onboard jumpers.
The recording length of 16-bit ADC data can be confgured via a jumper block. The available data length includes 4MB, 2MB, 512KB, 16KB, or 4KB.
The ADC-FIFO operation starts on one software instruction (set AST low) and stops automatically as soon as the selected recording length reached. The FIFO will retain this data until power-off, or a new ADC-FIFO operation is initiated.
The host controller can read any length of the FIFO but always starts at address zero.
SIGNALS
Two analog inputs INP and INN are differential signals direct routed to the chip, without buffer circuits. External user circuits driving the ADS1610 inputs must be able to handle the load presented by the switching capacitors within the chip.
Recommended circuit designs are available when using single-ended or differential op amps, respectively. The 16-bit ADC data is in binary two's complement. With the on- board (VREFP – VREFN)=VREF=3V, if INP>INN, outputs 0-0x7FFF, and if INP is less than INN, outputs are in the range 0x8000-0xFFFF.
The ADS1610 is a high-speed, 16-bit ADC designed for dynamic differential analog inputs other than precision still DC measurement. High speed sampling tends to be noisier. Special care must be taken when selecting the test equipment and setup used with this device.
EXPANSION
The GR16™ is designed as an expansion board, measuring 2.3 by 3.6 inches, for TERN 16-bit controllers such as A-Engine86, 586- Drive, EE, and FN. The GR16™ interfaces to Tern host controller via 20x2 pins at J1, and 10x2 pins at J2.
Multiple GR16™ units can be stacked sharing common CLK and SYNC signals. With the CLK inputs running, pulse SYNC, multiple converters will convert synchronously simultaneously.
